1. Field of the Invention
The present invention relates to a method for programming of a nonvolatile memory which includes an array of memory cells for storage of data on the basis of the number of carriers accumulated between the control gate and the channel region and particularly to a method for determining programming voltage in order to the optimum level of a drain voltage provided for programming the memory cells by hot carrier injection.
2. Description of the Related Art
A typical example of the nonvolatile memory is a flash erasable, electrically programmable read-only memory (flash EEPROM) including an electrically insulated MOS gate called a floating gate (see “A Single Transistor EEPROM Cell and Implementation in 512k CMOS EEPROM” by S. Mukherjee et. al, IEDM Technical Digest, p. 616, 1985).
FIG. 1 illustrates a memory cell structure of such a conventional flash EPROM. The structure has a layer arrangement where the floating gate 1 is disposed to control directly a channel 2 and store data (electrons) and a control gate 4 is stacked over the floating gate 1 via an insulating layer 3. As apparent from an equivalent circuit shown in FIG. 2, the floating gate 1 is isolated from the external terminals by the insulating layer and its potential is controllably determined by capacitance coupling of the four external terminals. As the data writing operation is based on the mechanism of hot carrier phenomenon which is equal to the principle of writing operation on an ultraviolet ray erasable EPROM, it allows the electrons to be loaded with a higher level of energy than the barrier height of a tunnel gate oxide layer 5 serving as the insulating layer and injected in the floating gate 1. The erasing operation based on the mechanism of Fowler-Nordheim tunnel phenomenon involves releasing the electrons across the tunnel oxide layer 5 of an overlap region between the floating gate 1 and the source diffusion 6. This can control the number of electrons in the floating gate 1. The reading operation which is equal to that of a common NOR type MOS memory involves sensing a difference in the driving current for the accumulated data (the number of electrons) in each memory cell selectively activated through the bit line (drain 7) and the word line (control gate 4).
When the hot carrier phenomenon is used as the mechanism of carrier injection, the current received by the floating gate 1 is expressed by the following equation (1), as described in the lucky electron model of “Solid-State Electron 2” by W. Shockley, 1961:Ig=Is×exp(−φb/Esd/λ)  (1)where Ig is the gate supplying current, Is is the source current, φb is the barrier height, Esd is the source/drain electric field, and λ is the scattering mean free path of hot electrons.
It is thus apparent that the hot carrier current (Ig) depends largely on the source/drain electrical field (Esd). In the actual memory cell array, the source/drain electrical field (Esd) is significantly affected by the drain source voltage, the load resistance in the drain current path, and the effective channel length in a memory cell transistor. Those parameters may be varied depending on the degree of process error in each memory array chip. It is hence necessary that the drain voltage provided by the control circuit for programming is set with its optimum level at each chip.
For the purpose, a method for measuring the program characteristics of the memory cell in each chip and determining an optimum of the programming voltage from the measurements is disclosed in Japanese Published Patent Publication No. 09-502828 (WO 95/07536). As disclosed in this publication, the method is adopted for determining the programming drain voltage in a nonvolatile memory. As shown in the flowchart of FIG. 3, the method comprises the steps of:
(a) determining a first value which presents the first level of the programming drain voltage;
(b) feeding a programming drain voltage generator circuit in the nonvolatile memory with the first value to generate the programming drain voltage from the first value;
(c) selecting a plurality of memory cells in the nonvolatile memory and applying the programming drain voltage to the plurality of the memory cells for a predetermined length of time for programming;
(d) measuring a threshold voltage at one of the memory cells of the group after the programming;
(e) comparing the measurement of the threshold voltage with a range of programmed threshold voltages in the nonvolatile memory;
(f) shifting the programming drain voltage by repeating the steps (b) to (e) with changing the first value to another when the measurement of the threshold voltage is out of the range of the programmed threshold voltages; and
(g) storing the first value in the nonvolatile memory for generating the programming drain voltage from the first value so that the nonvolatile memory is programmed with the range of the threshold voltages within the predetermined length of time for programming when the measurement of the threshold voltage remains within the range of the programmed threshold voltages and constantly controlling the programming drain voltage generator circuit.
As described, the conventional attempt determines the programming drain voltage so that the nonvolatile memory is programmed with the range of the threshold voltages within the predetermined length of time for programming but fails to discuss the following drawbacks.
More specifically, the load resistance developed in the path from the programming drain voltage generator circuit to each nonvolatile memory cell may be different depending on the location or address of a target point in the array of the nonvolatile memory cells. This is derived from the fact that the construction of interconnecting extending from the programming drain voltage generator circuit to the target nonvolatile memory cell is varied in the length and the material depending on the location or address of a target point in the array of the nonvolatile memory cells. In other words, when the programmable drain voltage is released at a uniform level from the programming drain voltage generator circuit, it may actually be varied from one memory cell to another by the effect of a change in the load resistance of the path or the current activating capability of the memory cell.
FIG. 4 illustrates the relationship between the drain voltage as a base data and the threshold voltage after programming according to the present invention. As shown, a curve (a) indicates that the threshold voltage after programming increases greater than the drain voltage does. Another curve (b) indicates that the threshold voltage after programming is moderately increased as compared with the drain voltage.
In the programming by hot carrier injection, the threshold voltage after programming depends mainly on three factors: (1) drain voltage, (2) gate voltage, and (3) log scale pulse time. When the programming pulse width is constant, the threshold voltage after application of the programming pulse is hardly affected by the threshold voltage prior to programming, provided that the threshold voltage before application of the programming pulse is not higher than the voltage level determined by the three factors. Whenever the erasing operation is inserted or not between any two adjacent writing operations with the drain voltage, the relationship shown in FIG. 4 remains the same.
The prior art allows the threshold voltage in the nonvolatile memory cell after programming to be significantly varied in response to an actual change in the programming drain voltage from one memory cell to another in a single chip when the programming drain voltage remains in a range denoted by the curve (a) even if it has been set to an initial level satisfying the programming time. This will cause variations in the programming speed, the threshold voltage after programming, and the margin of the reliability.